Y/C Progressive Display Horizontal Timing Example - Texas Instruments TMS320C64x DSP Reference Manual

Figure 4–37. Y/C Progressive Display Horizontal Timing Example
VCLKIN
4
FPCOUNT
IPCOUNT
VCTL1 (HBLNK) † §
VCTL1 (HSYNC) † §
VCLKOUT
VDOUT[9–0] §
VDOUT[19–0] §
EAV Blanking Data
FLCOUNT n – 1
FRMWIDTH = 1650 IMGHOFF1 = 8
HBLNKSTART = 1280 IMGHSIZE1 = 1264
HBLNKSTOP = 1646 IMGHOFF2 = n/a
IMGHSIZE2 = n/a
† Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00,
HBLNK output when VCTL1S bit is set 01.
‡ HBLNK operation when HBDLA bit in VDHBLNK is set to 1.
§ Diagram assumes a two VCLK pipeline delay between internal counters and output signals.
362 4
One Line
‡
Blanking
É É
É É
É É
SAV
n
HSYNCSTART = 1350
HSYNCSTOP = 1430
1280
Next Line
Display Image
Active Video
EAV
n + 1