Bt.656 Fifo Unpacking; Bit Bt.656 Fifo Unpacking - Texas Instruments TMS320C64x DSP Reference Manual

Dsp video port/vcxo interpolated control (vic) port
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4.2.4

BT.656 FIFO Unpacking

Display data is always packed into the FIFOs in 64-bit words and must be
unpacked before being sent to the video display data pipeline. The unpacking
and byte ordering is dependant upon the display data size and the device
endian mode. For little-endian operation (default), data is unpacked from right
to left; for big-endian operation, data is unpacked from left to right.
The 8-bit BT.656 mode uses three FIFOs for color separation. Four samples
are unpacked from each word as shown in Figure 4–12.
Figure 4–12. 8-Bit BT.656 FIFO Unpacking
VCLKOUT
Cb 0
VDOUT[9–2]
63
5655
Y 31
Y 30
Y 23
Y 22
Y 15
Y 14
Y 7
Y 6
Y FIFO
63
5655
Cb 15
Cb 14
Cb 7
Cb 6
Cb FIFO
63
5655
Cr 15
Cr 14
Cr 7
Cr 6
Cr FIFO
63
5655
Y 24
Y 25
Y 16
Y 17
Y 8
Y 9
Y 0
Y 1
Y FIFO
63
5655
Cb 8
Cb 9
Cb 0
Cb 1
Cb FIFO
63
5655
Cr 8
Cr 9
Cr 0
Cr 1
Cr FIFO
SPRU629
Y 0
Cr 0
Y 1
Cb 1
Y 2
4847
4039
32
31
Y 29
Y 28
Y 21
Y 20
Y 13
Y 12
Y 5
Y 4
4847
4039
3231
Cb 13
Cb 12
Cb 5
Cb 4
4847
4039
3231
Cr 13
Cr 12
Cr 5
Cr 4
Little-Endian Unpacking
4847
4039
32
31
Y 26
Y 27
Y 18
Y 19
Y 10
Y 11
Y 2
Y 3
4847
4039
3231
Cb 10
Cb 11
Cb 2
Cb 3
4847
4039
3231
Cr 10
Cr 11
Cr 2
Cr 3
Big-Endian Unpacking
BT.656 Video Display Mode
Cr 1
Y 3
Cb 2
Y 4
Cr 2
2423
1615
Y 27
Y 26
Y 25
Y 19
Y 18
Y 17
Y 11
Y 10
Y 9
Y 3
Y 2
Y 1
2423
1615
Cb 11
Cb 10
Cb 9
Cb 3
Cb 2
Cb 1
2423
1615
Cr 11
Cr 10
Cr 9
Cr 3
Cr 2
Cr 1
2423
1615
Y 28
Y 29
Y 30
Y 20
Y 21
Y 22
Y 12
Y 13
Y 14
Y 4
Y 5
Y 6
2423
1615
Cb 12
Cb 13
Cb 14
Cb 4
Cb 5
Cb 6
2423
1615
Cr 12
Cr 13
Cr 14
Cr 4
Cr 5
Cr 6
Video Display Port
Y 5
8 7
0
Y 24
Y 16
Y 8
Y 0
8 7
0
Cb 8
Cb 0
8 7
0
Cr 8
Cr 0
8 7
0
Y 31
Y 23
Y 15
Y 7
8 7
0
Cb 15
Cb 7
8 7
0
Cr 15
Cr 7
4-13

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