Video Port Pin Interrupt Clear Register (Piclr) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

GPIO Registers
Table 5–13. Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions
†
Bit field symval
31–23 Reserved –
22 PICLR22
NONE
VCTL3CLR
21 PICLR21
NONE
VCTL2CLR
20 PICLR20
NONE
VCTL1CLR
19–0 PICLR[19–0]
NONE
VDATAnCLR
† For CSL implementation, use the notation VP_PICLR_PICLRn_symval
5-26 General Purpose I/O Operation
†
Value Description
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
Allows PISTAT22 bit to be cleared to a logic low.
0 No effect.
1 Clears PISTAT22 (VCTL3) bit to 0.
Allows PISTAT21 bit to be cleared to a logic low.
0 No effect.
1 Clears PISTAT21 (VCTL2) bit to 0.
Allows PISTAT20 bit to be cleared to a logic low.
0 No effect.
1 Clears PISTAT20 (VCTL1) bit to 0.
Allows PISTAT[19–0] bit to be cleared to a logic low.
0 No effect.
1 Clears PISTAT[n] (VDATA[n]) bit to 0.
SPRU629