Data Receive Register (Drr); Data Receive Register (Drr) Field Descriptions - Texas Instruments TMS320C6000 Reference Manual

11.1

Data Receive Register (DRR)

Figure 48. Data Receive Register (DRR)
31
Legend: R = Read only; -n = value after reset
Table 20. Data Receive Register (DRR) Field Descriptions
Bit Field
symval
31−0 DR OF(value)
†
For CSL implementation, use the notation MCBSP_DRR_DR_symval.
SPRU580C
The data receive register (DRR) contains the value to be written to the data
bus. The DRR is shown in Figure 48 and described in Table 20.
For devices with an EDMA, DRR is mapped to memory locations on both the
EDMA bus (data port) as well as the peripheral bus (configuration bus). See
the device-specific datasheet for the memory address of these registers. DRR
is accessible via the peripheral bus and via the EDMA bus. Both the CPU and
the EDMA can access DRR in all the memory-mapped locations. An access
to any EDMA bus location is equivalent to an access to DRR of the
corresponding McBSP. For example, a read from any word-aligned address
in a DRR location on the EDMA bus is equivalent to a read from the DRR of
the corresponding McBSP on the peripheral bus. It is recommended that you
set up the EDMA to use the EDMA bus for serial port servicing in order to free
up the peripheral bus for other functions.
† Value Description
0−FFFF FFFFh Data receive register value to be written to the data bus.
DR
R-0
Multichannel Buffered Serial Port (McBSP)
Registers
0
87