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Table 4–20. Video Display Threshold Register (VDTHRLD) Field Descriptions
†
Bit
field
symval
31–26 Reserved
–
25–16 VDTHRLD2
OF(value)
15–12 INCPIX
OF(value)
11–10
Reserved
–
9–0
VDTHRLD1
OF(value)
† For CSL implementation, use the notation VP_VDTHRLD_field_symval
SPRU629
BT.656 and Y/C Mode
†
Value
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–3FFh
Field 2 threshold. Whenever
there are at least VDTHRLD
doublewords of space in the
Y display FIFO, a new Y
DMA event may be
generated. Whenever there
are at least ½ VDTHRLD
doublewords of space in the
Cb or Cr display FIFO, a
new Cb or Cr DMA event
may be generated.
0–Fh
Not used.
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0–3FFh
Field 1 threshold. Whenever
there are at least VDTHRLD
doublewords of space in the
Y display FIFO, a new Y
DMA event may be
generated. Whenever there
are at least ½ VDTHRLD
doublewords of space in the
Cb or Cr display FIFO, a
new Cb or Cr DMA event
may be generated.
Video Display Registers
Description
Raw Data Mode
Field 2 threshold. Whenever
there are at least VDTHRLD
doublewords of space in the
display FIFO, a new Y DMA
event may be generated.
FPCOUNT is incremented
every INCPIX output clocks.
Field 1 threshold. Whenever
there are at least VDTHRLD
doublewords of space in the
display FIFO, a new Y DMA
event may be generated.
Video Display Port
4-77
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