Video Port Pin Data Input Register (Pdin) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

GPIO Registers
Table 5–6. Video Port Pin Data Input Register (PDIN) Field Descriptions
†
Bit field symval
31–23 Reserved –
22 PDIN22
VCTL3LO
VCTL3HI
21 PDIN21
VCTL2LO
VCTL2HI
20 PDIN20
VCTL1LO
VCTL1HI
19–0 PDIN[19–0]
VDATAnLO
VDATAnHI
† For CSL implementation, use the notation VP_PDIN_PDINn_symval
5-12 General Purpose I/O Operation
†
Value Description
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
PDIN22 bit returns the logic level of the VCTL3 pin.
0 Pin is logic low.
1 Pin is logic high.
PDIN21 bit returns the logic level of the VCTL2 pin.
0 Pin is logic low.
1 Pin is logic high.
PDIN20 bit returns the logic level of the VCTL1 pin.
0 Pin is logic low.
1 Pin is logic high.
PDIN[19–0] bit returns the logic level of the corresponding
VDATA[n] pin.
0 Pin is logic low.
1 Pin is logic high.
SPRU629