Video Display Field 1 Vertical Blanking Start Register (Vdvblks1) - Texas Instruments TMS320C64x DSP Reference Manual

Figure 4–43. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
31 28 27
Reserved
R-0
15 12 11
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–10. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
Field Descriptions
†
Bit field
31–28 Reserved
27–16 VBLNKYSTART1
15–12 Reserved
11–0 VBLNKXSTART1
† For CSL implementation, use the notation VP_VDVBLKS1_field_symval
SPRU629
BT.656 and Y/C Mode
†
symval Value
– 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
OF(value) 0–FFFh Specifies the line (in
FLCOUNT) where
VBLNK active edge
occurs for field 1. Does
not affect EAV/SAV V bit
operation.
– 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
OF(value) 0–FFFh Specifies the pixel (in
FPCOUNT) where
VBLNK active edge
occurs for field 1.
Video Display Registers
VBLNKYSTART1
R/W-0
VBLNKXSTART1
R/W-0
Description
Raw Data Mode
Specifies the line (in
FLCOUNT) where vertical
blanking begins (VBLNK
active edge) for field 1.
Specifies the pixel (in
FPCOUNT) where
vertical blanking begins
(VBLNK active edge) for
field 1.
Video Display Port
16
0
4-63