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Video Capture Registers
Table 3–15. Video Capture Channel A Control Register (VCACTL)
Field Descriptions (Continued)
†
Bit
field
symval
30
BLKCAP
CLEAR
BLOCK
29–22 Reserved –
21
RDFE
DISABLE
ENABLE
20
FINV
FIELD1
FIELD2
19
EXC
EAVSAV
EXTERN
† For CSL implementation, use the notation VP_VCACTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.
3-54
Video Capture Port
†
Value
BT.656 or Y/C Mode
Block capture events bit. BLKCAP functions as a capture FIFO
reset without affecting the current programmable register values.
The F1C, F2C, and FRMC status bits, in VCASTAT, are not
updated. Field or frame complete interrupts and vertical interrupts
are also not generated.
Clearing BLKCAP does not enable DMA events during the field
where the bit is cleared. Whenever BLKCAP is set and then
cleared, the software needs to clear the field and frame status
bits (F1C, F2C, and FRMC) as part of the BLKCAP clear
operation.
0
Enables DMA events in the video frame that follows the video
frame where the bit is cleared. (The capture logic must sync to
the start of the next frame after BLKCAP is cleared.)
1
Blocks DMA events and flushes the capture channel FIFOs.
0
Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Field identification enable bit. (Channel A only)
0
Not used.
1
Not used.
Detected field invert bit.
0
Detected 0 is field 1.
1
Detected 0 is field 2.
External control select bit. (Channel A only)
0
Use EAV/SAV codes.
1
Use external control
signals.
Description
Raw Data Mode
TSI Mode
Field identification
Not used.
is disabled.
Field identification
Not used.
is enabled.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
SPRU629
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