Texas Instruments TMS320C64x DSP Reference Manual page 250

Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued)
†
Bit field symval
21 PDIR21
VCTL2IN
VCTL2OUT
20 PDIR20
VCTL1IN
VCTL1OUT
19–17 Reserved –
16 PDIR16
VDATA16TO19IN
VDATA16TO19OUT
15–13 Reserved –
12 PDIR12
VDATA12TO15IN
VDATA12TO15OUT
11 Reserved –
10 PDIR10
VDATA10TO11IN
VDATA10TO11OUT
9 Reserved –
† For CSL implementation, use the notation VP_PDIR_field_symval
SPRU629
†
Value Description
PDIR21 bit controls the direction of the VCTL2 pin.
0 Pin functions as input.
1 Pin functions as output.
PDIR20 bit controls the direction of the VCTL1 pin.
0 Pin functions as input.
1 Pin functions as output.
0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
PDIR16 bit controls the direction of the VDATA[19–16]
pins.
0 Pins function as input.
1 Pins function as output.
0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
PDIR12 bit controls the direction of the VDATA[15–12]
pins.
0 Pins function as input.
1 Pins function as output.
0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
PDIR10 bit controls the direction of the VDATA[11–10]
pins.
0 Pins function as input.
1 Pins function as output.
0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
GPIO Registers
General Purpose I/O Operation 5-9