Addressing Modes; Appendix B Table Of Machine Instructions Codes Appendix - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
BX and BY registers are allocated to the memory addresses FFECH (BX
register) and FFEDH (BY register) in the internal I/O address spaces.
Only their lower four bits are effective, with the upper four bits
being undefined. These undefined .bits are always set to "1" when reat
out. By resetting, the lower four bits of BX and BY registers are
initialized to "0".
BX I - I - I - I - IBX3IBX2IBXlIBXOI R/W
(FFECH) -------------------------------
BY I - I - I - I - IBY31BY21BYliBYOI R/W
(FFECH) -------------------------------
(6) SP register
SP register is a l6-bit register called a stack pointer (SP), that
stores the start address of the memory stack area (Last in, first out
basis). It is decremented when a CALL or PUSH instruction is executed
or an interrupt is accepted. It is incremented by execution of RET
instruction or a POP instruction.
(7)
PC register
This is a l6-bit register called a program counter, and stores the
memory address of the next instruction to be executed.
It is initialized to OOOOH when the RESET pin becomes low.
(8) Other
By executing the data exchange instruction [EXX] between a main
register and an alternative register, the EXF bit (exchange flag: Bit
1 of memory address FFD2H) of the internal I/O register is inverted.
This is a read-only bit, and is not initialized by resetting.
3.1.3 Addressing modes
Eight addressing modes are available for the TMP90C840. They are used
in combination with various instructions to enhance the CPU's
processing capabilities.
They are: Register mode, immediate mode, register indirect mode, index
mode, register index mode, extend mode, direct mode and relative mode.
The first seven addressing modes are used most frequently. The
relative addressing mode is only applicable to specific instructions.
(1) Register addressing mode
In the register addressing mode, the operand represents a specified
register.
Example: LD A, B
The contents of Register B are loaded into Register A.
(2) Immediate addressing mode
In this mode, the operand is in the instruction.
Example: LD A, 12H
Immediate data "12H" are loaded into Register A.
MPU90-l2