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[Automatic security bit programming/erasing]
Address
Security bit
Erasing
Security bit
programming
3.1.1.3. Area Address (AA), Block Address (BA): Code Flash
Table 2.2 to Table 2.5 show area addresses and block addresses. An address of the area or block to be erased should
be specified in the 6
th
single chip mode, an address of the mirror area should be specified.
3.1.1.4. Protect Bit Assignment (PBA): Code flash
A protect bit can be controlled in the unit of one bit.
"Table 3.4 Protect bit programming address" shows the protect bit selection of the automatic protect bit
programming.
FLASH
Area
Block
I/F
0
(Note)
0
0
1
2
3
4
5
6
7
8
2018-06-05
Adr
Adr
[31:24]
[23:19]
SBA: Address of
"00000"
0x5E
fixed
SBA: Address of
"00000"
0x5E
fixed
bus write cycle of automatic area erasing command and automatic block erasing command. In
Table 3.4 Protect bit programming address
Page
Register
0
1
2
3
[FCPSR0]
4
5
6
7
8 to 15
16 to 23
24 to 31
32 to 39
[FCPSR1]
40 to 47
48 to 55
56 to 63
64 to 71
Adr
Adr
[18:17]
[16:12]
the 6
th
bus write cycle of security bit erasing
"00"
"00001"
fixed
fixed
the 4
th
bus write cycle of security bit programming
"00"
"00001"
fixed
fixed
Protect
Adr
Adr
bit
[11:10]
[9]
<PG0>
00
0
<PG1>
00
0
<PG2>
00
0
<PG3>
00
0
<PG4>
00
0
<PG5>
00
0
<PG6>
00
0
<PG7>
00
0
<BLK1>
00
0
<BLK2>
00
0
<BLK3>
00
0
<BLK4>
00
0
<BLK5>
00
0
<BLK6>
00
0
<BLK7>
00
0
<BLK8>
00
0
34 / 120
Adr
[11:0]
"0"
Recommended
"0"
Recommended
PBA[11:4]
Adr
Adr
Adr
Adr
[8]
[7]
[6]
[5]
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
TXZ Family
Flash Memory
Example of
address
Adr
[31:0]
[4]
0
0x5E002000
1
0x5E002010
0
0x5E002020
1
0x5E002030
0
0x5E002040
1
0x5E002050
0
0x5E002060
1
0x5E002070
0
0x5E002080
1
0x5E002090
0
0x5E0020A0
1
0x5E0020B0
0
0x5E0020C0
1
0x5E0020D0
0
0x5E0020E0
1
0x5E0020F0
Rev. 2.0
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