Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 6

Contents
External Access Bus (EAB) .................................................... 2-10
Arbitration of the External Bus .............................................. 2-11
DEB/EAB Performance ......................................................... 2-11
MEMORY
Memory Architecture .................................................................... 3-1
L1 Instruction SRAM ................................................................... 3-5
L1 Data SRAM ............................................................................ 3-7
L1 Data Cache ............................................................................. 3-8
Boot ROM ................................................................................... 3-8
External Memory .......................................................................... 3-8
Processor-Specific MMRs .............................................................. 3-8
DMEM_CONTROL Register ................................................. 3-9
DTEST_COMMAND Register ............................................ 3-10
SYSTEM INTERRUPTS
Overview ...................................................................................... 4-1
Features .................................................................................. 4-1
Interfaces ...................................................................................... 4-2
Description of Operation .............................................................. 4-2
Events and Sequencing ............................................................ 4-2
System Peripheral Interrupts .................................................... 4-7
Programming Model ................................................................... 4-14
System Interrupt Initialization ............................................... 4-14
System Interrupt Processing Summary ................................... 4-14
vi ADSP-BF537 Blackfin Processor Hardware Reference