Chelsio Communications Terminator Series Installation And User Manual page 65

Unified wire for linux
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Chapter II. Network (NIC/TOE)
gives the following output in
[root@receiver_host~]# cat /proc/interrupts | grep eth6
Id
CPU0
36:
0
37:
0
38:
0
39:
1
Here there are 4 receiving queues from the eth6 interface, but they are not bound to a specific
CPU or interrupt entry. Queue 2 has caused a very large number of interrupts on CPU2 while
CPU0 and CPU1 are barely used by any of the four queues. Enabling RSS is thus essential for
best performance.
Linux's
irqbalance
Note
multiprocessor platform. However,
hardware devices across processors. For a server with Chelsio network card
constantly receiving large volume of data at 40/10Gbps, the network interrupt
demands are significantly high. Under such circumstances, it is necessary to enable
RSS to balance the network load across multiple processors and achieve the best
performance.
Interrupt Coalescing
The idea behind Interrupt Coalescing (IC) is to avoid flooding the host CPUs with too many
interrupts. Instead of throwing one interrupt per incoming packet, IC waits for 'n' packets to be
available in the Rx queues and placed into the host memory through DMA operations before an
interrupt is thrown, reducing the CPU load and thus improving latency. It can be changed using
the following command:
[root@host~]# ethtool –C ethX rx-frames n
For more information, run the following command:
Note
[root@host~]# ethtool -h
Large Receive Offload / Generic Receive Offload
Large Receive Offload or Generic Receive Offload is a performance improvement feature at the
receiving side. LRO/GRO aggregates the received packets that belong to same stream, and
combines them to form a larger packet before pushing them to the receive host network stack. By
Chelsio Unified Wire for Linux
/proc/interrupts
CPU1
CPU2
9
0
0
21718
7
391519
0
33
may take charge of distributing interrupts among CPUs on a
.
CPU3
type
17418
PCI-MSI-edge
2063
PCI-MSI-edge
222
PCI-MSI-edge
17798
PCI-MSI-edge
irqbalance
distributes interrupt requests from all
interface
eth6 (queue 0)
eth6 (queue 1)
eth6 (queue 2)
eth6 (queue 3)
65

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