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6.3.2 Vector Table
Vector table in the S1C17 Core
The table below lists the interrupts for which the vector table is referenced during interrupt handling.
Software interrupt No.
The vector address is one that contains a vector (or the jump address) for the user's interrupt handler routine
that is provided for each interrupt and is executed when the relevant interrupt occurs. Because an address value
is stored, each vector address is located at a 16-bit boundary. The memory area in which these vectors are
stored is referred to as the "vector table." The "TTBR" in the Vector Address column represents the base (start)
address of the vector table. For the TTBR value, refer to the Technical Manual of each model. The set value can
be read from TTBR (vector table base register) located at address 0xffff80.
6.3.3 Interrupt Handling
When an interrupt occurs, the processor starts interrupt handling. (This interrupt handling does not apply for reset
and debug interrupts.)
The interrupt handling performed by the processor is outlined below.
(1) Suspends the instructions currently being executed.
An interrupt is generated synchronously with the rising edge of the system clock at the end of the cycle of the
currently executed instruction.
(2) Saves the contents of the PC and PSR to the stack (SP), in that order.
(3) Clears the IE (interrupt enable) bit in the PSR to disable maskable interrupts that would occur thereafter. If
the generated interrupt is a maskable interrupt, the IL (interrupt level) in the PSR is rewritten to that of the
generated interrupt.
(4) Reads the vector for the generated interrupt from the vector table, and sets it in the PC. The processor thereby
branches to the user's interrupt handler routine.
After branching to the user's interrupt handler routine, when the reti instruction is executed at the end of interrupt
handling, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the
suspended instructions.
6.3.4 Reset
The processor is reset by applying a low-level pulse to its rst_n pin. All the registers are thereby cleared to 0.
The processor starts operating at the rising edge of the reset pulse to perform a reset sequence. In this reset
sequence, the reset vector is read out from the top of the vector table and set in the PC. The processor thereby
branches to the user's initialization routine, in which it starts executing the program. The reset sequence has priority
over all other processing.
S1C17 CORE MANUAL
(Rev. 1.2)
Table 6.3.2.1 Vector List
Vector No.
0 (0x00)
Reset
1 (0x01)
Address misaligned interrupt
2 (0x02)
NMI
3 (0x03)
Maskable external interrupt 3
:
31 (0x1f)
Maskable external interrupt 31
Seiko Epson Corporation
Interrupt
Vector address
TTBR + 0x00
TTBR + 0x04
TTBR + 0x08
TTBR + 0x0c
:
TTBR + 0x7c
6 FUNCTIONS
:
6-7
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