Extension Of Register Indirect Addressing With Displacement; Extension Of Signed Pc Relative Addressing - Epson S1C17 Series Manual

Cmos 16-bit single chip microcontroller
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5.3.4 Extension of Register Indirect Addressing with Displacement

Extending [%sp+imm7] displacement
The immediate (imm7) in displacement-added register indirect addressing instructions is extended.
The extended data and the SP are added to comprise the source or destination address of transfer.
Extending to a 20-bit immediate
To extend the immediate to 20-bit quantity, enter one ext instruction directly before the target instruction.
Example: ext
imm13
ld
%rd,[%sp+imm7]
SP
Immediate
Extending to a 24-bit immediate
To extend the immediate to 24-bit quantity, enter two ext instructions directly before the target instruction.
Example: ext
imm13 (1)
imm13 (2)
ext
ld
%rd,[%sp+imm7]
SP
Immediate

5.3.5 Extension of Signed PC Relative Addressing

Extending the displacement of PC relative branch instructions
The sign7 immediate in PC relative branch instructions is extended to a signed 21-bit or a signed 24-bit im-
mediate. The sign7 immediate in PC relative branch instructions is multiplied by 2 for conversion to a relative
value for the jump address, and the derived value is then added to PC to determine the jump address. The ext
instructions extend this relative jump address value.
Extending to a 21-bit immediate
To extend the sign7 immediate to a 21-bit immediate, enter one ext instruction directly before the target in-
struction.
Example: ext
imm13
jrgt
sign7
Immediate
PC
PC
The most significant bit "S" in the immediate that has been extended by the ext instruction is the sign, with
which bits 23–21 are extended to become signed 21-bit data. The most significant bit in sign7 is handled as the
MSB data of 7-bit data, and not as the sign.
S1C17 CORE MANUAL
(Rev. 1.2)
; = ld
23
23
20 19
0
0
0 0
imm13
; = ld
23
23
20 19
imm13
(1)
imm13 (2)
(3:0)
; = jrgt
23
21 20
S S S S
imm13
23
Current address
23
Seiko Epson Corporation
%rd,[%sp+imm20]
Stack pointer
+
7
6
%rd,[%sp+imm24]
Stack pointer
+
7
6
sign21
8 7
sign7
+
New address
5 INSTRUCTION SET
0
0
imm7
0
0
imm7
1
0
0
0
0
0
0
5-11

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