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jrge
sign7
jrge.d sign7
Function
Conditional PC relative jump (for judgment of signed operation results)
Standard)
Extension 1) pc ← pc + 2 + sign21 if !(N^V) is true
Extension 2) pc ← pc + 2 + sign24 if !(N^V) is true
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Code
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IL
IE
C
Flag
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–
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Mode
Signed PC relative
CLK
jrge
jrge.d
Description
(1) Standard
jrge
If the condition below has been met, this instruction doubles the signed 7-bit immediate sign7
and adds it to the PC (PC + 2) for branching the program flow to the address. It does not branch
if the condition has not been met.
• N flag = V flag (e.g. "A ≥ B" has resulted by cmp A,B)
The sign7 specifies a word address in 16-bit units.
The sign7 (×2) allows branches within the range of PC - 126 to PC + 128.
(2) Extension 1
ext
jrge
The ext instruction extends the displacement to be added to the PC (PC + 2) into signed 21
bits using its 13-bit immediate data imm13. The sign21 allows branches within the range of PC
- 1,048,574 to PC + 1,048,576.
(3) Extension 2
ext
ext
jrge
The ext instructions extend the displacement to be added to the PC (PC + 2) into signed 24
bits using their immediates (imm3 and imm13). The sign24 allows branches within the range of
PC - 8,388,606 to PC + 8,388,608.
(4) Delayed branch (d bit (bit 7) = 1)
jrge.d
For the jrge.d instruction, the next instruction becomes a delayed slot instruction. A delayed
slot instruction is executed before the program branches. Interrupts are masked in intervals
between the jrge.d instruction and the next instruction, so no interrupts occur.
Example
cmp
%r0,%r1
jrge
0x1
Caution
When the jrge.d instruction (delayed branch) is used, be careful to ensure that the next
instruction is limited to those that can be used as a delayed slot instruction. If any other instruction
is executed, the program may operate indeterminately. For the usable instructions, refer to the
instruction list in the Appendix.
S1C17 CORE MANUAL
(Rev. 1.2)
pc ← pc + 2 + sign7 × 2 if !(N^V) is true
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V
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N
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–
–
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Two cycles (when not branched), Three cycles (when branched)
Two cycles (when a one-cycle delayed slot instruction follows), Three cycles (other)
sign7
; = "jrge sign8", sign7 = sign8(7:1), sign8(0)=0
imm13
; = sign21(20:8)
sign7
; = "jrge sign21", sign7 = sign21(7:1), sign21(0)=0
imm3
; imm3(2:0)= sign24(23:21)
imm13
; = sign24(20:8)
sign7
; = "jrge sign24", sign7 = sign24(7:1), sign24(0)=0
sign7
; r0 and r1 contain signed data.
; Skips the next instruction if r0 ≥ r1.
Seiko Epson Corporation
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sign7
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sign7
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7 DETAILS OF INSTRUCTIONS
jrge
jrge.d
7-43
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