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7 DETAILS OF INSTRUCTIONS
jpa
%rb
jpa.d %rb
Function
Unconditional PC absolute jump
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
0
|
|
0
0
0
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
PC absolute
CLK
jpa
jpa.d
Description
(1) Standard
jpa
The content of the rb register is loaded to the PC, and the program branches to that address. The
LSB of the rb register is ignored and is always handled as 0.
(2) Delayed branch (d bit (bit 7) = 1)
jpa.d
For the jpa.d instruction, the next instruction becomes a delayed slot instruction. A delayed
slot instruction is executed before the program branches. Interrupts are masked in intervals
between the jpa.d instruction and the next instruction, so no interrupts occur.
Example
jpa
%r0 ; Jumps to the address specified by the r0 register.
Caution
When the jpa.d instruction (delayed branch) is used, be careful to ensure that the next instruction
is limited to those that can be used as a delayed slot instruction. If any other instruction is executed,
the program may operate indeterminately. For the usable instructions, refer to the instruction list in
the Appendix.
7-38
pc ← rb
9
8
7
6
|
0
0
0
0
1
0
1
|
|
|
|
|
|
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0
0
0
0
1
1
1
|
|
|
|
|
|
V
Z
N
|
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|
–
–
–
Three cycles
Two cycles (when a one-cycle delayed slot instruction follows), Three cycles (other)
%rb
%rb
Seiko Epson Corporation
5
4
3
2
1
0
|
0
0
1
r b
|
|
|
|
|
|
0
0
1
r b
|
|
|
|
|
jpa
jpa.d
S1C17 CORE MANUAL
(REV. 1.2)
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