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ld.ub %rd, [%sp + imm7]
Function
Unsigned byte data transfer
Standard)
Extension 1) rd(7:0) ← B[sp + imm20], rd(15:8) ← 0, rd(23:16) ← 0
Extension 2) rd(7:0) ← B[sp + imm24], rd(15:8) ← 0, rd(23:16) ← 0
15 14 13 12 11 10
Code
1
1
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Register indirect with displacement
Dst: Register direct %rd = %r0 to %r7
CLK
Two cycles
Description
(1) Standard
ld.ub
The byte data in the specified memory location is transferred to the rd register after being zero-
extended to 16 bits. The content of the current SP with the 7-bit immediate imm7 added as
displacement comprises the memory address to be accessed. The eight high-order bits of the rd
register are set to 0.
(2) Extension 1
ext
ld.ub
The ext instruction extends the displacement to a 20-bit quantity. As a result, the content of
the SP with the 20-bit immediate imm20 added comprises the memory address, the byte data in
which is transferred to the rd register after being zero-extended to 16 bits. The eight high-order
bits of the rd register are set to 0.
(3) Extension 2
ext
ext
ld.ub
The two ext instructions extend the displacement to a 24-bit quantity. As a result, the content
of the SP with the 24-bit immediate imm24 added comprises the memory address, the byte data
in which is transferred to the rd register after being zero-extended to 16 bits. The eight high-
order bits of the rd register are set to 0.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
ext
ld.ub
S1C17 CORE MANUAL
(Rev. 1.2)
rd(7:0) ← B[sp + imm7], rd(15:8) ← 0, rd(23:16) ← 0
9
8
7
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0
0
1
r d
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V
Z
N
|
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–
–
–
%rd,[%sp + imm7]
imm13
%rd,[%sp + imm7]
imm4
imm13
%rd,[%sp + imm7]
0x1
%r0,[%sp + 0x1] ; r0 ← [sp + 0x81] zero-extended
Seiko Epson Corporation
6
5
4
3
2
1
0
imm7
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; memory address = sp + imm7
; = imm20(19:7)
; memory address = sp + imm20,
; imm7 = imm20(6:0)
; imm4(3:0) = imm24(23:20)
; = imm24(19:7)
; memory address = sp + imm24,
; imm7 ← imm24(6:0)
7 DETAILS OF INSTRUCTIONS
7-107
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