6.2.2 Execution Cycles and Flags
The following shows the number of cycles required for executing each instruction in a 1-cycle accessible memory
connected to the Harvard bus and the flag change status.
Depending on the model, clock cycles spent by the external bus arbiter and wait cycles inherent in the external
devices may be added.
Table 6.2.2.1 Number of Instruction Execution Cycles and Flag Status
Classification
Data transfer
ld.b
ld.ub
ld
ld.a
S1C17 CORE MANUAL
(Rev. 1.2)
Mnemonic
Cycle
1
%rd,%rs
*1
1–2
%rd,[%rb]
2
%rd,[%rb]+
2
%rd,[%rb]-
2
%rd,-[%rb]
2
%rd,[%sp+imm7]
1
%rd,[imm7]
*1
1–2
[%rb],%rs
2
[%rb]+,%rs
2
[%rb]-,%rs
2
-[%rb],%rs
2
[%sp+imm7],%rs
1
[imm7],%rs
1
%rd,%rs
*1
1–2
%rd,[%rb]
2
%rd,[%rb]+
2
%rd,[%rb]-
2
%rd,-[%rb]
2
%rd,[%sp+imm7]
1
%rd,[imm7]
1
%rd,%rs
1
%rd,sign7
*1
1–2
%rd,[%rb]
2
%rd,[%rb]+
2
%rd,[%rb]-
2
%rd,-[%rb]
2
%rd,[%sp+imm7]
1
%rd,[imm7]
*1
1–2
[%rb],%rs
2
[%rb]+,%rs
2
[%rb]-,%rs
2
-[%rb],%rs
2
[%sp+imm7],%rs
1
[imm7],%rs
1
%rd,%rs
1
%rd,imm7
*1
1–2
%rd,[%rb]
2
%rd,[%rb]+
2
%rd,[%rb]-
2
%rd,-[%rb]
2
%rd,[%sp+imm7]
1
%rd,[imm7]
*1
1–2
[%rb],%rs
2
[%rb]+,%rs
2
[%rb]-,%rs
2
-[%rb],%rs
2
[%sp+imm7],%rs
1
[imm7],%rs
1
%rd,%sp
1
%rd,%pc
*1
1–2
%rd,[%sp]
2
%rd,[%sp]+
2
%rd,[%sp]-
2
%rd,-[%sp]
Seiko Epson Corporation
Flag
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6 FUNCTIONS
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6-3