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ld.b [%sp + imm7], %rs
Function
Signed byte data transfer
Standard)
Extension 1) B[sp + imm20] ← rs(7:0)
Extension 2) B[sp + imm24] ← rs(7:0)
15 14 13 12 11 10
Code
1
1
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register indirect with displacement
CLK
Two cycles
Description
(1) Standard
ld.b
The eight low-order bits of the rs register are transferred to the specified memory location. The
content of the current SP with the 7-bit immediate imm7 added as displacement comprises the
memory address to be accessed.
(2) Extension 1
ext
ld.b
The ext instruction extends the displacement to a 20-bit quantity. As a result, the eight low-
order bits of the rs register are transferred to the address indicated by the content of the SP with
the 20-bit immediate imm20 added.
(3) Extension 2
ext
ext
ld.b
The two ext instructions extend the displacement to a 24-bit quantity. As a result, the eight
low-order bits of the rs register are transferred to the address indicated by the content of the SP
with the 24-bit immediate imm24 added.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
ext
0x1
ld.b
[%sp + 0x1],%r0
S1C17 CORE MANUAL
(Rev. 1.2)
B[sp + imm7] ← rs(7:0)
9
8
7
6
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1
0
0
r s
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V
Z
N
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–
–
–
[%sp + imm7],%rs
imm13
[%sp + imm7],%rs
imm4
imm13
[%sp + imm7],%rs
; B[sp + 0x81] ← 8 low-order bits of r0
Seiko Epson Corporation
5
4
3
2
1
0
imm7
|
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; memory address = sp + imm7
; = imm20(19:7)
; memory address = sp + imm20,
; imm7 = imm20(6:0)
; imm4(3:0) = imm24(23:20)
; = imm24(19:7)
; memory address = sp + imm24,
; imm7 = imm24(6:0)
7 DETAILS OF INSTRUCTIONS
7-95
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