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sub.a %rd, imm7
Function
24-bit subtraction
Standard)
Extension 1) rd(23:0) ← rd(23:0) - imm20(zero extended)
Extension 2) rd(23:0) ← rd(23:0) - imm24
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Code
0
1
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Immediate data (unsigned)
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
sub.a
The 7-bit immediate imm7 is subtracted from the rd register after being zero-extended.
(2) Extension 1
ext
sub.a
The 20-bit immediate imm20 is subtracted from the rd register after being zero-extended.
(3) Extension 2
ext
ext
sub.a
The 24-bit immediate imm24 is subtracted from the rs register.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
(1) sub.a
(2) ext
ext
sub.a
S1C17 CORE MANUAL
(Rev. 1.2)
rd(23:0) ← rd(23:0) - imm7(zero extended)
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7
6
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0
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r d
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V
Z
N
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–
–
–
; rd ← rd - imm7
%rd,imm7
imm13
; = imm20(19:7)
; rd ← rd - imm20, imm7 = imm20(6:0)
%rd,imm7
imm4
; imm4(3:0) = imm24(23:20)
imm13
; = imm24(19:7)
; rd ← rd - imm24, imm7 = imm24(6:0)
%rd,imm7
%r0,0x7f
; r0 = r0 - 0x7f
0xf
0x1fff
%r1,0x7f
; r1 = r1 - 0xffffff
Seiko Epson Corporation
5
4
3
2
1
0
imm7
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7 DETAILS OF INSTRUCTIONS
7-129
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