Ld.a %Rd, [%Sp + Imm7] - Epson S1C17 Series Manual

ld.a %rd, [%sp + imm7]

Function 32-bit data transfer
Standard)
Extension 1) rd(23:0) ← A[sp + imm20](23:0), ignored ← A[sp + imm20](31:24)
Extension 2) rd(23:0) ← A[sp + imm24](23:0), ignored ← A[sp + imm24](31:24)
15 14 13 12 11 10
Code
1 1 1
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IL IE C
Flag
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– – –
Mode Src: Register indirect with displacement
Dst: Register direct %rd = %r0 to %r7
CLK Two cycles
Description (1) Standard
ld.a
The 32-bit data (the eight high-order bits are ignored) in the specified memory location is
transferred to the rd register. The content of the current SP with the 7-bit immediate imm7
added as displacement comprises the memory address to be accessed.
(2) Extension 1
ext
ld.a
The ext instruction extends the displacement to a 20-bit quantity. As a result, the content of the
SP with the 20-bit immediate imm20 added comprises the memory address, the 32-bit data (the
eight high-order bits are ignored) in which is transferred to the rd register.
(3) Extension 2
ext
ext
ld.a
The two ext instructions extend the displacement to a 24-bit quantity. As a result, the content
of the SP with the 24-bit immediate imm24 added comprises the memory address, the 32-bit
data (the eight high-order bits are ignored) in which is transferred to the rd register.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
ext 0x1
ld.a %r0,[%sp + 0x4]
Caution
The SP and the displacement must specify a 32-bit boundary address (two least significant bits =
0). Specifying other address causes an address misaligned interrupt. Note, however, that the data
transfer is performed by setting the two least significant bits of the address to 0.
S1C17 CORE MANUAL
(Rev. 1.2)
rd(23:0) ← A[sp + imm7](23:0), ignored ← A[sp + imm7](31:24)
9 8 7 6
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0 1 1 r d
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V Z N
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– – –
%rd,[%sp + imm7]
imm13
%rd,[%sp + imm7]
imm4
imm13
%rd,[%sp + imm7]
; r0 ← [sp + 0x84]
Seiko Epson Corporation
5 4 3 2 1 0
imm7
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; memory address = sp + imm7
; = imm20(19:7)
; memory address = sp + imm20,
; imm7 = imm20(6:0)
; imm4(3:0) = imm24(23:20)
; = imm24(19:7)
; memory address = sp + imm24,
; imm7 = imm24(6:0)
7 DETAILS OF INSTRUCTIONS
7-73