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5 INSTRUCTION SET
5.7 Shift and Swap Instructions
The S1C17 Core supports instructions to shift or swap the register data.
Logical shift right
sr
Logical shift left (= Arithmetic shift left)
sl
Arithmetic shift right
sa
Swap upper and lower bytes
swap
The shift operation is effective for bits 15 to 0 in the specified register and bits 23 to 16 are set to 0.
The number of bits to be shifted can be specified to 0–3 bits, 4 bits, or 8 bits using the operand imm5 or the rs reg-
ister.
%rs/imm7 = 0–3:
Shift 0 to 3 bits
%rs/imm7 = 4–7:
Shift 4 bits (fixed)
%rs/imm7 = 8 or more: Shift 8 bits (fixed)
Example: sr
%rd,1
sl
%rd,7
sa
%rd,0xf
sr Logical shift right
sl Logical shift left
sa Arithmetic shift right
The swap instruction replaces the contents of general-purpose registers with each other, as shown below.
rs
rd
5-16
Bits 15–0 in %rd logically shifted one bit to the right
Bits 15–0 in %rd logically shifted four bits to the left
Bits 15–0 in %rd arithmetically shifted eight bits to the right
23
0
0
0
0
0
0
23
0
0
0
0
0
0
23
0
0
0
0
0
0
23
16
15
X
X
X
X
X
X
X X
23
16
0
0
0
0
0
0
0 0
15
Seiko Epson Corporation
rd
16
15
0 0
0
rd
16
15
0 0
C
rd
16
15
0 0
MSB
Sign bit
8 7
Byte 1
Byte 0
Byte 0
Byte 1
8 7
0
C
0
0
0
C
0
0
S1C17 CORE MANUAL
(REV. 1.2)
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