Intl Imm5, Imm3 - Epson S1C17 Series Manual

Cmos 16-bit single chip microcontroller
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intl imm5, imm3

Function
Software interrupt with interrupt level setting
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
1
1
|
|
IL
IE
C
Flag
|
|
↔ 0
Mode
Immediate data (unsigned)
CLK
Three cycles
Description
Generates the interrupt of the vector number specified with the imm5.
The intl instruction saves the address of the next instruction and the contents of the PSR into the
stack, then reads the specified interrupt vector from the vector table and sets it to the PC. By this
processing, the program flow branches to the specified interrupt handler routine. In addition to this,
the imm3 value is set to the IL bits in the PSR (interrupt level) to disable interrupts of which the
interrupt level is lower than the imm3 while the interrupt handler routine is executed.
The altered IL bits are restored to the value before the intl instruction is executed when the
interrupt handler routine is terminated by the reti instruction.
Example
intl
0x3,0x2
S1C17 CORE MANUAL
(Rev. 1.2)
sp ← sp - 4, A[sp] ← {psr, pc + 2}, pc ← TTBR + (vector No. = imm5) × 4,
psr(IL) ← imm3
9
8
7
6
|
|
1
0
1
imm3
|
|
|
|
|
V
Z
N
|
|
|
; Generates an external maskable interrupt 0x3
; and set the IL bits to 0x2.
Seiko Epson Corporation
5
4
3
2
1
0
|
imm5
1
1
|
|
|
|
|
7 DETAILS OF INSTRUCTIONS
7-37

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