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7 DETAILS OF INSTRUCTIONS
sub.a
%rd, %rs
sub.a/c
%rd, %rs
sub.a/nc %rd, %rs
24-bit subtraction
Function
Standard)
Extension 1) rd(23:0) ← rs(23:0) - imm13(zero extended)
Extension 2) rd(23:0) ← rs(23:0) - imm24
15 14 13 12 11 10
Code
0
0
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
sub.a
The content of the rs register is subtracted from the rd register.
(2) Extension 1
ext
sub.a
The 13-bit immediate imm13 is subtracted from the content of the rs register after being zero-
extended, and the result is loaded into the rd register. The content of the rs register is not
altered.
(3) Extension 2
ext
ext
sub.a
The 24-bit immediate imm24 is subtracted from the content of the rs register, and the result is
loaded into the rd register. The content of the rs register is not altered.
(4) Conditional execution
The /c or /nc suffix on the opcode specifies conditional execution.
sub.a/c
sub.a/nc Executed as sub.a when the C flag is 0 or executed as nop when the flag is 1
In this case, the ext instruction can be used to extend the operand.
(5) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
(1) sub.a
(2) ext
ext
sub.a
7-128
rd(23:0) ← rd(23:0) - rs(23:0)
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1
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1
r d
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1
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r d
0
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1
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r d
0
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V
Z
N
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–
–
–
; rd ← rd - rs
%rd,%rs
imm13
; rd ← rs - imm13
%rd,%rs
imm11
; imm11(10:0) = imm24(23:13)
imm13
; = imm24(12:0)
; rd ← rs - imm24
%rd,%rs
Executed as sub.a when the C flag is 1 or executed as nop when the flag is 0
%r0,%r0
; r0 = r0 - r0
0x7ff
0x1fff
%r1,%r2
; r1 = r2 - 0xffffff
Seiko Epson Corporation
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2
1
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0
r s
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r s
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1
1
0
r s
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sub.a
sub.a/c
sub.a/nc
S1C17 CORE MANUAL
(REV. 1.2)
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