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ld.a %sp, imm7
Function
24-bit data transfer
Standard)
Extension 1) sp(19:2) ← imm20(19:2), sp(23:20) ← 0, sp(1:0) ← 0
Extension 2) sp(23:2) ← imm24(23:2), sp(1:0) ← 0
15 14 13 12 11 10
Code
1
0
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Immediate data (unsigned)
Dst: Register direct %sp
CLK
One cycle
Description
(1) Standard
ld.a
The 7-bit immediate imm7 is loaded to the SP after being zero-extended.
(2) Extension 1
ext
ld.a
The immediate data is extended into a 20-bit quantity by the ext instruction and it is loaded to
the SP after being zero-extended.
(3) Extension 2
ext
ext
ld.a
The immediate data is extended into a 24-bit quantity by the ext instruction and it is loaded to
the SP.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
ext
0x8
ld.a
%sp,0x0
Caution
In data transfer to the SP, the low-order two bits of the source data are always handled as 0.
S1C17 CORE MANUAL
(Rev. 1.2)
sp(6:2) ← imm7(6:2), sp(23:7) ← 0, sp(1:0) ← 0
9
8
7
6
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1
1
1
0
0
0
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V
Z
N
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–
–
–
; sp ← imm7 (zero-extended)
%sp,imm7
imm13
; = sign20(19:7)
; sp ← imm20 (zero-extended),
%sp,imm7
; imm7 = imm20(6:0)
imm4
; imm4(3:0) = imm24(23:20)
imm13
; = imm24(19:7)
; sp ← imm24, imm7 = imm24(6:0)
%sp,imm7
; sp ← 0x400
Seiko Epson Corporation
5
4
3
2
1
0
imm7
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7 DETAILS OF INSTRUCTIONS
7-77
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