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7 DETAILS OF INSTRUCTIONS
not
%rd, %rs
not/c
%rd, %rs
not/nc %rd, %rs
Function
16-bit logical negation
Standard)
Extension 1) rd(15:0) ← !imm13(zero extended), rd(23:16) ← 0
Extension 2) rd(15:0) ← !imm16, rd(23:16) ← 0
15 14 13 12 11 10
Code
0
0
1
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0
0
1
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0
0
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
not
The low-order 16 bits of the rs register are reversed, and the result is loaded into the rd register.
The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0.
(2) Extension 1
ext
not
All the bits of the zero-extended 13-bit immediate imm13 are reversed after zero-extended into
16 bits, and the result is loaded into the rd register. The operation is performed in 16-bit size,
and bits 23–16 of the rd register are set to 0.
(3) Extension 2
ext
ext
not
All the bits of the 16-bit immediate imm16 are reversed, and the result is loaded into the rd
register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0.
(4) Conditional execution
The /c or /nc suffix on the opcode specifies conditional execution.
not/c
not/nc Executed as not when the C flag is 0 or executed as nop when the flag is 1
In this case, the ext instruction can be used to extend the operand.
(5) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
When r1 = 0x555555
not
%r0,%r1
7-110
rd(15:0) ← !rs(15:0), rd(23:16) ← 0
9
8
7
6
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0
1
1
r d
1
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0
1
1
0
r d
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0
1
1
r d
0
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V
Z
N
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0 ↔ ↔
; rd ← !rs
%rd,%rs
imm13
; rd ← !imm13
%rd,%rs
imm3
; imm3(2:0) = imm16(15:13)
imm13
; = imm16(12:0)
; rd ← !imm16
%rd,%rs
Executed as not when the C flag is 1 or executed as nop when the flag is 0
; r0 = 0x00aaaa
Seiko Epson Corporation
5
4
3
2
1
0
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0
1
1
r s
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0
1
1
r s
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1
1
1
r s
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not
not/c
not/nc
S1C17 CORE MANUAL
(REV. 1.2)
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