Power-Down Mode - Epson S1C17 Series Manual

6 FUNCTIONS

6.4 Power-Down Mode

The S1C17 Core supports two power-down modes: HALT and SLEEP modes.
HALT mode
Program execution is halted at the same time that the S1C17 Core executes the halt instruction, and the
processor enters HALT mode.
HALT mode commonly turns off only the S1C17 Core operation, note, however that modules to be turned off
depend on the implementation of the clock control circuit outside the core. Refer to the technical manual of
each model for details.
SLEEP mode
Program execution is halted at the same time the S1C17 Core executes the slp instruction, and the processor
enters SLEEP mode.
SLEEP mode commonly turns off the S1C17 Core and on-chip peripheral circuit operations, thereby it
significantly reduces the current consumption in comparison to HALT mode. However, modules to be turned
off depend on the implementation of the clock control circuit outside the core. Refer to the technical manual of
each model for details.
Canceling HALT or SLEEP mode
Initial reset is one cause that can bring the processor out of HALT or SLEEP mode. Other causes depend on the
implementation of the clock control circuit outside the S1C17 Core.
Initial reset, maskable external interrupts, NMI, and debug interrupts are commonly used for canceling HALT
and SLEEP modes.
The interrupt enable/disable status set in the processor does not affect the cancellation of HALT or SLEEP
mode even if an interrupt signal is used as the cancellation. In other words, interrupt signals are able to cancel
HALT and SLEEP modes even if the IE flag in PSR or the interrupt enable bits in the interrupt controller
(depending on the implementation) are set to disable interrupts.
When the processor is taken out of HALT or SLEEP mode using an interrupt that has been enabled (by the
interrupt controller and IE flag), the corresponding interrupt handler routine is executed after executing the
instruction next to the halt or slp instruction.
When the interrupt has been disabled, the processor restarts the program from the instruction next to halt or
slp after the processor is taken out of HALT or SLEEP mode.
6-10
Seiko Epson Corporation
S1C17 CORE MANUAL
(REV. 1.2)