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1 Summary .......................................................................................................................1-1
1.1 Features ...........................................................................................................................1-1
2 Registers .......................................................................................................................2-1
2.1 General-Purpose Registers (R0-R7) ...............................................................................2-1
2.2 Program Counter (PC) .....................................................................................................2-1
2.3 Processor Status Register (PSR) .....................................................................................2-2
2.4 Stack Pointer (SP) ............................................................................................................2-4
2.4.1 About the Stack Area .........................................................................................2-4
2.4.2 SP Operation at Subroutine Call/Return ............................................................2-4
2.4.3 SP Operation when an Interrupt Occurs ............................................................2-5
2.4.4 Saving/Restoring Register Data Using a Load Instruction ................................2-6
2.5 Register Notation and Register Numbers ........................................................................2-7
2.5.1 General-Purpose Registers ...............................................................................2-7
2.5.2 Special Registers ...............................................................................................2-7
3 Data Formats .................................................................................................................3-1
3.1 Data Formats Handled in Operations Between Registers................................................3-1
3.1.1 Unsigned 8-Bit Transfer (Register → Register) ..................................................3-1
3.1.2 Signed 8-Bit Transfer (Register → Register) ......................................................3-1
3.1.3 16-Bit Transfer (Register → Register) ................................................................3-2
3.1.4 24-Bit Transfer (Register → Register) ................................................................3-2
3.2 Data Formats Handled in Operations Between Memory and a Register .........................3-2
3.2.1 Unsigned 8-Bit Transfer (Memory → Register) ..................................................3-3
3.2.2 Signed 8-Bit Transfer (Memory → Register) ......................................................3-3
3.2.3 8-Bit Transfer (Register → Memory) ..................................................................3-3
3.2.4 16-Bit Transfer (Memory → Register) ................................................................3-3
3.2.5 16-Bit Transfer (Register → Memory) ................................................................3-4
3.2.6 32-Bit Transfer (Memory → Register) ................................................................3-4
3.2.7 32-Bit Transfer (Register → Memory) ................................................................3-4
4 Address Map .................................................................................................................4-1
4.1 Address Space .................................................................................................................4-1
4.2 Processor Information in the Core I/O Area ....................................................................4-2
4.2.1 Vector Table Base Register (TTBR, 0xffff80) .....................................................4-2
4.2.2 Processor ID Register (IDIR, 0xffff84) ...............................................................4-2
4.2.3 Debug RAM Base Register (DBRAM, 0xffff90) ..................................................4-2
5 Instruction Set ..............................................................................................................5-1
5.1 List of Instructions ............................................................................................................5-1
5.2 Addressing Modes (without ext extension) .....................................................................5-5
5.2.1 Immediate Addressing .......................................................................................5-5
5.2.2 Register Direct Addressing ................................................................................5-5
5.2.3 Register Indirect Addressing ..............................................................................5-6
5.2.5 Register Indirect Addressing with Displacement................................................5-7
5.2.6 Signed PC Relative Addressing ........................................................................5-7
5.2.7 PC Absolute Addressing ....................................................................................5-7
S1C17 CORE MANUAL
(Rev. 1.2)
- Contents -
Seiko Epson Corporation
CONTENTS
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