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and
%rd, %rs
and/c
%rd, %rs
and/nc %rd, %rs
Function
16-bit logical AND
Standard)
Extension 1) rd(15:0) ← rs(15:0) & imm13(zero extended), rd(23:16) ← 0
Extension 2) rd(15:0) ← rs(15:0) & imm16, rd(23:16) ← 0
15 14 13 12 11 10
Code
0
0
1
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0
0
1
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0
0
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
and
The content of the rs register and that of the rd register are logically AND'ed, and the result is
loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd
register are set to 0.
(2) Extension 1
ext
and
The content of the rs register and the zero-extended 13-bit immediate imm13 are logically
AND'ed, and the result is loaded into the rd register. The operation is performed in 16-bit size,
and bits 23–16 of the rd register are set to 0. The content of the rs register is not altered.
(3) Extension 2
ext
ext
and
The content of the rs register and the 16-bit immediate imm16 are logically AND'ed, and the
result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of
the rd register are set to 0. The content of the rs register is not altered.
(4) Conditional execution
The /c or /nc suffix on the opcode specifies conditional execution.
and/c
and/nc Executed as and when the C flag is 0 or executed as nop when the flag is 1
In this case, the ext instruction can be used to extend the operand.
(5) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
(1) and
(2) ext
ext
and
S1C17 CORE MANUAL
(Rev. 1.2)
rd(15:0) ← rd(15:0) & rs(15:0), rd(23:16) ← 0
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0
1
1
r d
1
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0
1
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0
r d
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0
1
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r d
0
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V
Z
N
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0 ↔ ↔
; rd ← rd & rs
%rd,%rs
imm13
; rd ← rs & imm13
%rd,%rs
imm3
; imm3(2:0) = imm16(15:13)
imm13
; = imm16(12:0)
; rd ← rs & imm16
%rd,%rs
Executed as and when the C flag is 1 or executed as nop when the flag is 0
%r0,%r0
; r0 = r0 & r0
0x1
0x1fff
%r1,%r2
; r1 = r2 & 0x3fff
Seiko Epson Corporation
5
4
3
2
1
0
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0
0
0
r s
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0
0
0
r s
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1
0
0
r s
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7 DETAILS OF INSTRUCTIONS
and
and/c
and/nc
7-11
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