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(2) Standard (example of post-increment option)
ld.a
The content of the rs register (24-bit data) is transferred to the specified memory location. The
SP contains the memory address to be accessed. This instruction writes 32-bit data with the
eight high-order bits set to 0 in the memory. The memory address will be incremented by two
bytes after the data transfer has finished.
(3) Extension 1 (example of post-decrement option)
ext
ld.a
The content of the rs register (24-bit data) is transferred to the specified memory location.
The SP contains the memory address to be accessed. This instruction writes 32-bit data with
the eight high-order bits set to 0 in the memory. The memory address will be decremented by
imm13 bytes after the data transfer has finished.
(4) Extension 2 (example of pre-decrement option)
ext
ext
ld.a
After the memory address specified by the SP is decremented by imm24 bytes, the content of
the rs register (24-bit data) is transferred to the decremented address. This instruction writes 32-
bit data with the eight high-order bits set to 0 in the memory.
(5) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Caution
The SP and the immediate value must specify a 32-bit boundary address (two least significant bits
= 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data
transfer is performed by setting the two least significant bits of the address to 0.
S1C17 CORE MANUAL
(Rev. 1.2)
[%sp]+,%rs
; Destination memory address = sp
; post increment: sp + 4
imm13
[%sp]-,%rs
; Destination memory address = sp
; post decrement: sp - imm13
imm11
; imm11(10:0) = imm24(23:13)
imm13
; = imm24(12:0)
-[%sp],%rs
; Destination memory address = sp - imm24
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7 DETAILS OF INSTRUCTIONS
7-83
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