Ld [%Rb], %Rs - Epson S1C17 Series Manual

Cmos 16-bit single chip microcontroller
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ld [%rb], %rs

Function
16-bit data transfer
Standard)
Extension 1) W[rb + imm13] ← rs(15:0)
Extension 2) W[rb + imm24] ← rs(15:0)
15 14 13 12 11 10
Code
0
0
1
|
|
IL
IE
C
Flag
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|
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register indirect %rb = %r0 to %r7
CLK
One cycle (two cycles when the ext instruction is used)
Description
(1) Standard
ld
[%rb],%rs
The 16 low-order bits of the rs register are transferred to the specified memory location. The rb
register contains the memory address to be accessed.
(2) Extension 1
ext
ld
The e x t instruction changes the addressing mode to register indirect addressing with
displacement. As a result, the 16 low-order bits of the rs register are transferred to the address
indicated by the content of the rb register with the 13-bit immediate imm13 added. The content
of the rb register is not altered.
(3) Extension 2
ext
ext
ld
The addressing mode changes to register indirect addressing with displacement, so the 16 low-
order bits of the rs register are transferred to the address indicated by the content of the rb
register with the 24-bit immediate imm24 added. The content of the rb register is not altered.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Caution
The rb register and the displacement must specify a 16-bit boundary address (least significant bit =
0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data
transfer is performed by setting the least significant bit of the address to 0.
S1C17 CORE MANUAL
(Rev. 1.2)
W[rb] ← rs(15:0)
9
8
7
6
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0
0
1
r s
0
|
|
|
|
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V
Z
N
|
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|
; memory address = rb
imm13
[%rb],%rs
; memory address = rb + imm13
imm11
; imm11(10:0) = imm24(23:13)
imm13
; = imm24(12:0)
[%rb],%rs
; memory address = rb + imm24
Seiko Epson Corporation
5
4
3
2
1
0
|
0
1
0
r b
|
|
|
|
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7 DETAILS OF INSTRUCTIONS
7-59

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