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5 INSTRUCTION SET
5.11 Coprocessor Instructions
The S1C17 Core incorporates a coprocessor interface and provides the dedicated coprocessor instructions listed be-
low.
Transfer data to the coprocessor
ld.cw
Transfer data and input the results and flag status to/from the coprocessor
ld.ca
Input flag status from the coprocessor
ld.cf
The ld.cw and ld.ca instructions send two 24-bit data set in the rd (data 0) and rs (data 1) registers to the copro-
cessor. Data 1 can also be specified in an immediate imm7. In this case, the 7-bit immediate can be extended into
imm20 or imm24 using the ext instruction.
The ld.ca instruction inputs the results from the coprocessor to the rd register.
The ld.ca and ld.cf instructions input the flag status from the coprocessor and set it to the PSR (C, V, Z, and N
flags).
The concrete commands and status of the coprocessor vary with each coprocessor connected to the chip. Refer to
the user's manual for the coprocessor used.
5-24
Seiko Epson Corporation
S1C17 CORE MANUAL
(REV. 1.2)
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