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Classification
Shift and swap
sr
sa
sl
swap
Immediate extension
ext
Conversion
cv.ab
cv.as
cv.al
cv.la
cv.ls
Branch
jpr
jpr.d
jpa
ipa.d
jrgt
jrgt.d
jrge
jrge.d
jrlt
jrlt.d
jrle
jrle.d
jrugt
jrugt.d
jruge
jruge.d
jrult
jrult.d
jrule
jrule.d
jreq
jreq.d
jrne
jrne.d
call
call.d
calla
calla.d
ret
ret.d
int
intl
reti
reti.d
brk
retd
System control
nop
halt
slp
ei
di
Coprocessor control
ld.cw
ld.ca
ld.cf
* The ld.a instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the
32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memo-
ry, the eight high-order bits of the read data are ignored.
S1C17 CORE MANUAL
(Rev. 1.2)
Mnemonic
Logical shift to the right with the number of bits specified by the register
%rd,%rs
Logical shift to the right with the number of bits specified by immediate
%rd,imm7
Arithmetic shift to the right with the number of bits specified by the register
%rd,%rs
Arithmetic shift to the right with the number of bits specified by immediate
%rd,imm7
Logical shift to the left with the number of bits specified by the register
%rd,%rs
Logical shift to the left with the number of bits specified by immediate
%rd,imm7
Bytewise swap on byte boundary in 16 bits
%rd,%rs
Extend operand in the following instruction
imm13
Convert signed 8-bit data into 24 bits
%rd,%rs
Convert signed 16-bit data into 24 bits
%rd,%rs
Convert 32-bit data into 24 bits
%rd,%rs
Converts 24-bit data into 32 bits
%rd,%rs
Converts 16-bit data into 32 bits
%rd,%rs
PC relative jump
sign10
Delayed branching possible
%rb
Absolute jump
imm7
Delayed branching possible
%rb
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative conditional jump
sign7
Delayed branching possible
PC relative subroutine call
sign10
Delayed call possible
%rb
Absolute subroutine call
imm7
Delayed call possible
%rb
Return from subroutine
Delayed return possible
Software interrupt
imm5
Software interrupt with interrupt level setting
imm5,imm3
Return from interrupt handling
Delayed call possible
Debug interrupt
Return from debug processing
No operation
HALT mode
SLEEP mode
Enable interrupts
Disable interrupts
Transfer data to coprocessor
%rd,%rs
%rd,imm7
Transfer data to coprocessor and get results and flag statuses
%rd,%rs
%rd,imm7
Transfer data to coprocessor and get flag statuses
%rd,%rs
%rd,imm7
Seiko Epson Corporation
5 INSTRUCTION SET
Function
Branch condition: !Z & !(N ^ V)
Branch condition: !(N ^ V)
Branch condition: N ^ V
Branch condition: Z | N ^ V
Branch condition: !Z & !C
Branch condition: !C
Branch condition: C
Branch condition: Z | C
Branch condition: Z
Branch condition: !Z
5-3
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