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(5) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
(1) cmp.a
(2) ext
ext
cmp.a
S1C17 CORE MANUAL
(Rev. 1.2)
%r0,%r1
; Changes the flags according to the results of
; r0 - r1.
0x1
0x1fff
%r1,%r2
; Changes the flags according to the results of
; r2 - 0x3fff.
Seiko Epson Corporation
7 DETAILS OF INSTRUCTIONS
7-25
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