Cv.ab %Rd, %Rs - Epson S1C17 Series Manual

cv.ab %rd, %rs

Function Data conversion from byte to 24 bits
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0 0 1
| |
IL IE C
Flag
| |
– – –
Mode Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK One cycle
Description (1) Standard
The eight low-order bits of the rs register are transferred to the rd register after being sign-
extended to 24 bits.
(2) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after a
branch instruction with the "d" bit.
Example When the R1 register contains 0x80
cv.ab
S1C17 CORE MANUAL
(Rev. 1.2)
rd(23:8) ← rs(7), rd(7:0) ← rs(7:0)
9 8 7
| |
0 1 0 r d
| | | | |
V Z N
| | |
– – –
23
rs X
23
rd S S S S S S S S
%r0,%r1 ; r0 = 0xffff80
Seiko Epson Corporation
6 5 4 3 2 1 0
|
0 1 1 1 r s
| | | | |
8 7
S
8 7
S S S S S S S S S
7 DETAILS OF INSTRUCTIONS
0
Byte
0
8 bits
7-27