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jpr
sign10
jpr.d sign10
Function
Unconditional PC relative jump
Standard)
Extension 1) pc ← pc + 2 + sign24
Extension 2) Unusable
15 14 13 12 11 10
Code
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IL
IE
C
Flag
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–
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Mode
Signed PC relative
CLK
jpr
jpr.d
Description
(1) Standard
jpr
Doubles the signed 10-bit immediate sign10 and adds it to the PC (PC + 2). The program flow
branches to the address. The sign10 specifies a word address in 16-bit units.
The sign10 (×2) allows branches within the range of PC - 1,022 to PC + 1,024.
(2) Extension 1
ext
jpr
The ext instruction extends the displacement to be added to the PC (PC + 2) into 24 bits using
its 13-bit immediate imm13.
The sign24 allows branches within the range of PC - 8,388,606 to PC + 8,388608.
(3) Delayed branch (d bit (bit 10) = 1)
jpr.d
For the jpr.d instruction, the next instruction becomes a delayed slot instruction. A delayed
slot instruction is executed before the program branches. Interrupts are masked in intervals
between the jpr.d instruction and the next instruction, so no interrupts occur.
Example
ext
0x20
jpr
0x00 ; Jumps to the address specified by pc + 2 + 0x10000.
Caution
When the jpr.d instruction (delayed branch) is used, be careful to ensure that the next instruction
is limited to those that can be used as a delayed slot instruction. If any other instruction is executed,
the program may operate indeterminately. For the usable instructions, refer to the instruction list in
the Appendix.
S1C17 CORE MANUAL
(Rev. 1.2)
pc ← pc + 2 + sign10 × 2
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Three cycles
Two cycles (when a one-cycle delayed slot instruction follows), Three cycles (other)
sign10
; = "jp sign11", sign10 = sign11(10:1), sign11(0)=0
imm13
; = sign24(23:11)
sign10
; = "jpr sign24", sign10 = sign24(10:1), sign24(0)=0
sign10
Seiko Epson Corporation
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sign10
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sign10
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7 DETAILS OF INSTRUCTIONS
jpr
jpr.d
7-41
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