Jreq Sign7; Jreq.d Sign7 - Epson S1C17 Series Manual

7 DETAILS OF INSTRUCTIONS
jreq sign7

jreq.d sign7

Function Conditional PC relative jump
Standard)
Extension 1) pc ← pc + 2 + sign21 if Z is true
Extension 2) pc ← pc + 2 + sign24 if Z is true
15 14 13 12 11 10
Code
0 0 0
| |
0 0 0
| |
IL IE C
Flag
| |
– – –
Mode Signed PC relative
CLK
jreq
jreq.d
Description
(1) Standard
jreq
If the condition below has been met, this instruction doubles the signed 7-bit immediate sign7
and adds it to the PC (PC + 2) for branching the program flow to the address. It does not branch
if the condition has not been met.
• Z flag = 1 (e.g. "A = B" has resulted by cmp A,B)
The sign7 specifies a word address in 16-bit units.
The sign7 (×2) allows branches within the range of PC - 126 to PC + 128.
(2) Extension 1
ext
jreq
The ext instruction extends the displacement to be added to the PC (PC + 2) into signed 21
bits using its 13-bit immediate data imm13. The sign21 allows branches within the range of PC
- 1,048,574 to PC + 1,048,576.
(3) Extension 2
ext
ext
jreq
The ext instructions extend the displacement to be added to the PC (PC + 2) into signed 24
bits using their immediates (imm3 and imm13). The sign24 allows branches within the range of
PC - 8,388,606 to PC + 8,388,608.
(4) Delayed branch (d bit (bit 7) = 1)
jreq.d
For the jreq.d instruction, the next instruction becomes a delayed slot instruction. A delayed
slot instruction is executed before the program branches. Interrupts are masked in intervals
between the jreq.d instruction and the next instruction, so no interrupts occur.
Example
cmp %r0,%r1
jreq 0x1
Caution When the jreq.d instruction (delayed branch) is used, be careful to ensure that the next
instruction is limited to those that can be used as a delayed slot instruction. If any other instruction
is executed, the program may operate indeterminately. For the usable instructions, refer to the
instruction list in the Appendix.
7-42
pc ← pc + 2 + sign7 × 2 if Z is true
9 8 7 6
|
0 1 1 1 0 0
| | | | | |
|
0 1 1 1 0 1
| | | | | |
V Z N
| | |
– – –
Two cycles (when not branched), Three cycles (when branched)
Two cycles (when a one-cycle delayed slot instruction follows), Three cycles (other)
sign7 ; = "jreq sign8", sign7 = sign8(7:1), sign8(0)=0
imm13 ; = sign21(20:8)
sign7 ; = "jreq sign21", sign7 = sign21(7:1), sign21(0)=0
imm3 ; imm3(2:0)= sign24(23:21)
imm13 ; = sign24(20:8)
sign7 ; = "jreq sign24", sign7 = sign24(7:1), sign24(0)=0
sign7
; Skips the next instruction if r1 = r0.
Seiko Epson Corporation
5 4 3 2 1 0
sign7
| | | | | |
sign7
| | | | | |
jreq
jreq.d
S1C17 CORE MANUAL
(REV. 1.2)