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7 DETAILS OF INSTRUCTIONS
sr %rd, %rs
Function
Logical shift to the right
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
1
|
|
IL
IE
C
Flag
|
|
– ↔ – ↔ ↔
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
The rd register is shifted as shown in the diagram below.
The number of bits to be shifted is specified by the rs register value as follows:
rs = 0–3:
rs = 4–7:
rs = 8 or more: 8 bits
Data "0" is placed in the bit 15 of the rd register. The operation is performed in 16-bit size, and
bits 23–16 of the rd register are set to 0.
rd register
(after execution)
(2) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after a
branch instruction with the "d" bit included.
7-124
Shift the content of rd to right as many bits as specified by rs (0–3, 4, or 8 bits),
MSB ← 0
9
8
7
6
|
|
0
1
1
r d
1
|
|
|
|
|
V
Z
N
|
|
|
0–3 bits
4 bits
23
X
X
X
X
X
X
0
0
0
0
0
0
Seiko Epson Corporation
5
4
3
2
1
0
|
1
0
0
r s
|
|
|
|
|
16
15
X X
0
0 0
0
0
C
C
S1C17 CORE MANUAL
(REV. 1.2)
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