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7 DETAILS OF INSTRUCTIONS
di
Function
Disable interrupts
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
0
|
|
IL
IE
C
Flag
|
|
–
0
–
Mode
–
CLK
One cycle
Description
(1) Standard
Resets the IE bit in the PSR to disable external maskable interrupts.
The reset interrupt, address misaligned interrupt, and NMI will be accepted even if the IE bit is
set to 0.
(2) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after a
branch instruction with the "d" bit.
Example
di
Caution
Maskable interrupts are disabled from the third cycle after the di instruction has been executed.
di
Instruction 1
Instruction 2
Instruction 3
Example: Interrupt disabled periods using the di and ei instructions
ld %r2,%r3
di
ld.a %r0,%r1
ld.b %r2,%r3
ld %r4,%r5
ei
add %r4,%r5
sub %r6,%r7
cmp %r0,%r1
7-32
psr(IE) ← 0
9
8
7
6
|
0
0
0
0
0
0
1
|
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
; Disables external maskable interrupts.
← 1-cycle instruction
← 1-cycle instruction
← Interrupts are disabled from this instruction.
← Interrupt enabled
← Interrupt enabled
← Interrupt enabled
← Interrupt enabled
← Interrupt disabled
← Interrupt disabled
← Interrupt disabled
← Interrupt disabled
← Interrupt enabled
Seiko Epson Corporation
5
4
3
2
1
0
0
0
0
0
0
0
|
|
|
|
|
|
S1C17 CORE MANUAL
(REV. 1.2)
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