Epson S1C17 Series Manual page 196

Data Transfer Instructions (2)
Mnemonic
Opcode Operand MSB
ld [%sp+imm7], %rs 1 1 1 1
[imm7], %rs 1 1 0 1
ld.a %rd, %rs 0 0 1 0
%rd, imm7 1 0 0 1
%rd, [%rb] 0 0 1 0
%rd, [%rb]+ 0 0 1 0
%rd, [%rb]- 0 0 1 0
%rd, -[%rb] 0 0 1 0
%rd, [%sp+imm7] 1 1 1 0
%rd, [imm7] 1 1 0 0
[%rb], %rs 0 0 1 0
[%rb]+, %rs 0 0 1 0
[%rb]-, %rs 0 0 1 0
-[%rb], %rs 0 0 1 0
[%sp+imm7], %rs 1 1 1 1
[imm7], %rs 1 1 0 1
%rd, %sp 0 0 1 1
%rd, %pc (*7) 0 0 1 1
%rd, [%sp] 0 0 1 1
%rd, [%sp]+ 0 0 1 1
%rd, [%sp]- 0 0 1 1
%rd, -[%sp] 0 0 1 1
[%sp], %rs 0 0 1 1
[%sp]+, %rs 0 0 1 1
[%sp]-, %rs 0 0 1 1
-[%sp], %rs 0 0 1 1
%sp, %rs 0 0 1 1
%sp, imm7 1 0 1 1
Remarks
*1) With one EXT: base address = rb+imm13, With two EXT: base address = rb+imm24
*2) With one EXT: data = sign16
*3) With one EXT: data = imm20, With two EXT: data = imm24
*4) With one EXT: base address = imm20, With two EXT: base address = imm24
*5) With one EXT: base address = sp+imm20, With two EXT: base address = sp+imm24
*6) With one EXT: base address = rb, address increment/decrement rb/sp ← rb/sp±imm13, With two EXT: base address = rb, address increment/decrement rb/sp ← rb/sp±imm24
*7) The "ld.a %rd, %pc" instruction should be used as a delayed slot instruction for the jr*.d, jpr.d, or jpa.d delayed branch instruction.
*8 ) With no EXT: 1 cycle, With EXT: 2 cycles
Code
LSB
1 0 rs imm7 W[sp+imm7]←rs(15:0)
1 0 rs imm7 W[imm7]←rs(15:0)
1 0 rd 0 0 1 1 rs rd(23:0)←rs(23:0)
1 1 rd imm7 rd(6:0)←imm7(6:0), rd(23:7)←0
0 0 rd 0 0 1 1 rb rd(23:0)←A[rb](23:0), ignored←A[rb](31:24)
0 0 rd 0 1 1 1 rb rd(23:0)←A[rb](23:0), ignored←A[rb](31:24), rb(23:0)←rb(23:0)+4
0 0 rd 1 1 1 1 rb rd(23:0)←A[rb](23:0), ignored←A[rb](31:24), rb(23:0)←rb(23:0)-4
rd rb
0 0 1 0 1 1 rb(23:0)←rb(23:0)-4, rd(23:0)←A[rb](23:0), ignored←A[rb](31:24)
1 1 rd imm7 rd(23:0)←A[sp+imm7](23:0), ignored←A[sp+imm7](31:24)
1 1 rd imm7 rd(23:0)←A[imm7](23:0), ignored←A[imm7](31:24)
0 1 rs 0 0 1 1 rb A[rb](23:0)←rs(23:0), A[rb](31:24)←0
0 1 rs 0 1 1 1 rb A[rb](23:0)←rs(23:0), A[rb](31:24)←0, rb(23:0)←rb(23:0)+4
0 1 rs 1 1 1 1 rb A[rb](23:0)←rs(23:0), A[rb](31:24)←0, rb(23:0)←rb(23:0)-4
0 1 rs 1 0 1 1 rb rb(23:0)←rb(23:0)-4, A[rb](23:0)←rs(23:0), A[rb](31:24)←0
1 1 rs imm7 A[sp+imm7](23:0)←rs(23:0), A[sp+imm7](31:24)←0
1 1 rs imm7 A[imm7](23:0)←rs(23:0), A[imm7](31:24)←0
1 1 rd 0 0 1 0 0 0 0 rd(23:2)←sp(23:2), rd(1:0)←0
1 1 rd 0 1 1 0 0 0 0 rd(23:0)←pc(23:0)+2
1 1 rd 0 0 1 1 0 0 0 rd(23:0)←A[sp](23:0), ignored←A[sp](31:24)
1 1 rd 0 1 1 1 0 0 0 rd(23:0)←A[sp](23:0), ignored←A[sp](31:24), sp(23:0)←sp(23:0)+4
1 1 rd 1 1 1 1 0 0 0 rd(23:0)←A[sp](23:0), ignored←A[sp](31:24), sp(23:0)←sp(23:0)-4
1 1 rd 1 0 1 1 0 0 0 sp(23:0)←sp(23:0)-4, rd(23:0)←A[sp](23:0), ignored←A[sp](31:24)
1 1 rs 0 0 1 1 1 0 0 A[sp](23:0)←rs(23:0), A[sp](31:24)←0
1 1 rs 0 1 1 1 1 0 0 A[sp](23:0)←rs(23:0), A[sp](31:24)←0, sp(23:0)←sp(23:0)+4
1 1 rs 1 1 1 1 1 0 0 A[sp](23:0)←rs(23:0), A[sp](31:24)←0, sp(23:0)←sp(23:0)-4
1 1 rs 1 0 1 1 1 0 0 sp(23:0)←sp(23:0)-4, A[sp](23:0)←rs(23:0), A[sp](31:24)←0
1 1 rs 1 0 1 0 0 0 0 sp(23:2)←rs(23:2), sp(1:0)←0
1 1 0 0 0 imm7 sp(6:2)←imm7(6:2), sp(23:7)←0, sp(1:0)←0
Function
S1C17 Core Instruction Set
Flags
Cycle EXT D
IL IE C V Z N
*5
2 – – – – – –
1 – – – – – – *4
1 – – – – – – –
1 – – – – – – *3
1, 2 *8 – – – – – – *1
2 – – – – – – *6
2 – – – – – – *6
*6
2 – – – – – –
*5
2 – – – – – –
*4
1 – – – – – –
*8 *1
1, 2 – – – – – –
*6
2 – – – – – –
*6
2 – – – – – –
*6
2 – – – – – –
*5
2 – – – – – –
*4
1 – – – – – –
1 – – – – – – –
1 – – – – – – –
*8 *1
1, 2 – – – – – –
*6
2 – – – – – –
*6
2 – – – – – –
*6
2 – – – – – –
*8 *1
1, 2 – – – – – –
2 – – – – – – *6
2 – – – – – – *6
2 – – – – – – *6
1 – – – – – – –
1 – – – – – – *3