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7 DETAILS OF INSTRUCTIONS
sl %rd, imm7
Function
Logical shift to the left
Standard)
Extension 1) imm7 is extended to imm20
Extension 2) imm7 is extended to imm24
15 14 13 12 11 10
Code
1
0
1
|
|
IL
IE
C
Flag
|
|
– ↔ – ↔ ↔
–
Mode
Src: Immediate (unsigned)
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
The rd register is shifted as shown in the diagram below.
The number of bits to be shifted is specified by the 7-bit immediate imm7 as follows:
imm7 = 0–3:
imm7 = 4–7:
imm7 = 8 or more: 8 bits
Data "0" is placed in the least significant bit of the rd register. The operation is performed in 16-
bit size, and bits 23–16 of the rd register are set to 0.
rd register
(after execution)
(2) Extension
Using the ext instruction extends the 7-bit immediate imm7 to 20-bit immediate imm20 or 24-
bit immediate imm24. However, there is no difference in operation from the standard instruction
without extension.
(3) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after a
branch instruction with the "d" bit included. In this case, extension of the immediate by the ext
instruction cannot be performed.
7-122
Shift the content of rd to left as many bits as specified by imm7 (0–3, 4, or 8 bits),
LSB ← 0
9
8
7
6
|
|
1
1
0
r d
|
|
|
|
|
V
Z
N
|
|
|
0–3 bits
4 bits
23
X
X
X
X
X
X
0
0
0
0
0
0
Seiko Epson Corporation
5
4
3
2
1
0
imm7
|
|
|
|
|
|
16
15
X X
0 0
0
0
0
S1C17 CORE MANUAL
(REV. 1.2)
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