Intel Agilex Configuration User Manual page 37

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
high. In addition, the host must handle backpressure by monitoring the
signal any time after the assertion of
configuration.
Note: For Avalon-ST x16 and x32, after Power-On-Reset you must not send data to the device until it indicates it is ready using
. You must drive
nSTATUS
to go high. The device can starting sending data when
nSTATUS
The
AVST_READY
To configure the Intel Agilex device successfully, the host must adhere to the following constraints:
•
The host must drive no more than six data words after the deassertion of the
incurred by the 2-stage register synchronizer.
•
The host must synchronize the
Register transfer level (RTL) example code for 2-stage register synchronizer:
always @(posedge avst_clk or negedge reset_n)
begin
if (~reset_n)
begin
else
end
end
Where:
— The
AVST_CLK
—
fpga_avst_ready
—
fpga_avst_ready_reg2
You must properly constrain the
between the host and Intel Agilex device to ensure the Avalon-ST configuration timing specifications are met. Refer to the
Avalon-ST Configuration Timing section of the Intel Agilex Device Data Sheet for information about the timing specifications.
Note:
The signal must run continuously during configuration. The
AVST_CLK
running.
Send Feedback
AVST_READY
low and wait for
nCONFIG
signal sent by the Intel Agilex device to the host is not synchronized with the
AVST_READY
fpga_avst_ready_reg1 <= 0;
fpga_avst_ready_reg2 <= 0;
fpga_avst_ready_reg1 <= fpga_avst_ready;
fpga_avst_ready_reg2 <= fpga_avst_ready_reg1;
signal comes from either PFL II IP or your Avalon-ST controller logic.
is the signal from the Intel Agilex device.
AVST_READY
signal is the
AVST_READY
and
AVST_CLK AVST_DATA
AVST_READY
signal. The host must monitor the
to go low. Next, you should drive
nSTATUS
AVSTx8_READY
signal to the signal using a 2-stage register synchronizer. Here is
AVST_CLK
signal that is synchronous to
signals at the host. Perform timing analysis on both signals
AVST_READY
signal and may assert
AVST_VALID
signal throughout the
AVST_READY
high and wait for
nCONFIG
asserts.
or
AVSTx8_CLK
signal including the delay
AVST_READY
.
AVST_CLK
signal cannot assert unless the clock is
Intel ® Agilex ™ Configuration User Guide
.
AVST_CLK
37