Intel Agilex Configuration User Manual page 51

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
3.1.6.3. PFL II Signals
Table 16. PFL II Signals
Pin
pfl_nreset
pfl_flash_access_granted
pfl_clk
fpga_pgm[]
fpga_conf_done
fpga_nstatus
pfl_nreconfigure
Send Feedback
Type Weak Pull-Up
Input — Asynchronous reset for the PFL II IP core. Pull high to enable FPGA
configuration. To prevent FPGA configuration, pull low when you do not
use the PFL II IP core. This pin does not affect the PFL II IP flash
programming functionality.
Input — For system-level synchronization. A processor or any arbiter that controls
access to the flash drives this input pin. To use the PFL II IP core function
as the flash master pull this pin high. Driving the
pfl_flash_access_granted
accessing the flash and FPGA configuration.
Input — User input clock for the device. This is the frequency you specify for the
What is the external clock frequency? parameter on the Configuration
tab of the PFL II IP. This frequency must not be higher than the maximum
DCLK
available if you are only using the PFL II IP for flash programming.
Input — Determines the page for the configuration. This pin is not available if you
are only using the PFL II IP for flash programming.
Input 10 kΩ Pull-Up
Connects to the
Resistor
high if the configuration is successful. During FPGA configuration, this pin
remains low. This pin is not available if you are only using the PFL II IP for
flash programming.
Input 10 kΩ Pull-Up
Connects to the
Resistor
FPGA configuration begins and must stay high during FPGA configuration.
If a configuration error occurs, the FPGA pulls this pin low and the PFL II
IP core stops reading the data from the flash memory device. This pin is
not available if you are only using the PFL II IP for flash programming.
Input — When low initiates FPGA reconfiguration. To implement manual control of
reconfiguration connect this pin to a switch. You can use this input to write
your own logic in a CPLD to trigger reconfiguration via the PFL II IP. When
FPGA reconfiguration begins, the
the FPGA device. The
available if you are only using the PFL II IP for flash programming.
Function
pin low prevents the JTAG interface from
frequency you specify for FPGA during configuration. This pin is not
pin of the FPGA. The FPGA releases the pin
CONF_DONE
pin of the FPGA. This pin is high before the
nSTATUS
fpga_nconfig
pin registers this signal. This pin is not
pfl_clk
Intel ® Agilex
pin is pulled low to reset
continued...
™ Configuration User Guide
51