Intel Agilex Configuration User Manual page 47

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
Figure 18. Cypress and Micron M28, M29 Flash Memory in 16-Bit Mode
The address bit numbers in the PFL II IP core and the flash memory device are the same.
3.1.6.1.3. Implementing Multiple Pages in the Flash .pof
The PFL II IP core stores configuration data in a maximum of eight pages in a flash memory block.
The total number of pages and the size of each page depends on the flash density. Here are some guidelines for storing your
designs to pages:
• Always store designs for different FPGA chains on different pages.
• You may choose store different designs for a FPGA chain on a single page or on multiple pages.
• When you choose to store the designs for a FPGA chain on a single page, the design order must match the JTAG chain
device order.
Use the generated
to conversion:
.pof
• Block mode—allows you to specify the start and end addresses for the page.
• Start mode—allows you to specify only the start address. The start address for each page must be on an 8 KB boundary.
If the first valid start address is
• Auto mode—allows the Intel Quartus Prime software to automatically determine the start address of the page. The Intel
Quartus Prime software aligns the pages on a 128 KB boundary. If the first valid start address is
start address is an multiple of
Send Feedback
address: 23 bits
PFL II
to create a flash memory device
.sof
, the next valid start address is an increment of
0×000000
.
0x20000
address: 23 bits
Flash Memory
22 22
21 21
20 20
- -
- -
- -
2 2
1 1
0 0
. The following address modes are available for the
.pof .sof
.
0×2000
, the next valid
0x000000
Intel ® Agilex ™ Configuration User Guide
47