Intel Agilex Configuration User Manual page 79

4. Intel Agilex Configuration Features
UG-20205 | 2019.04.03
Figure 34. Intel Agilex CvP Configuration Block Diagram
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V
CCIO_SDM
Configuration
10kΩ 10kΩ
Control Signals
Optional
Monitoring
MSEL
AS x4 Flash Memory
DATA[3:0]
DCLK
nCS0
Periphery
Image (.jic)
PCIe Host
Root
Complex
n
Core Image
3
2
Core Image 1
(.rbf)
Intel FPGA
CVP_CONFDONE (optional)
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
3
MSEL[2:0]
Configuration
Control Signals
4
AS_DATA[3:0]
AS_CLK
AS_nCS0
PCIe Link
PCIe
End
Hard IP
Point
(HIP)
Update via
PCIe Link
FPGA Fabric
Core Image
Secure
Device
Manager
Intel ® Agilex ™ Configuration User Guide
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