Intel Agilex Configuration User Manual page 29

2. Intel Agilex Configuration Details
UG-20205 | 2019.04.03
•
CONF_DONE
•
INIT_DONE
•
HPS_COLD_nRESET
•
PWRMGT_SCL
•
PWRMGT_SDA
•
PWRMGT_ALERT
•
DATA UNLOCK
With the exception of the partial reconfiguration signals,
SDM I/O pins to the configuration pins without dedicated pin assignments. You can only use GPIOs for
, and
PR_ERROR
Reconfiguration External Configuration Controller Intel Agilex FPGA IP.
Table 6. Intel Agilex Device Configuration Pins
Configuration Function
(3)
TCK
(3)
TDI
(3)
TMS
(3)
TDO
nSTATUS
nCONFIG
(4)
MSEL[2:0]
(5)
CONF_DONE
(3)
The JTAG pins can access the HPS JTAG chain in Intel Agilex SoC devices.
(4)
The pins are dual purpose. You can assign any unused
MSEL[2:0]
non-dedicated configuration pins.
Send Feedback
pins by specifying them in the Intel Quartus Prime software and connecting them to the Partial
PR_DONE
Configuration Scheme
All schemes
All schemes
All schemes
All schemes
,
PR_REQUEST PR_ERROR
JTAG
JTAG
JTAG
JTAG
pin to other functions such as power management or
MSEL[2:0]
, and , you can assign the unused
PR_DONE
PR_REQUEST
Direction Powered by
Input V
CCIO_SDM
Input V
CCIO_SDM
Input V
CCIO_SDM
Output V
CCIO_SDM
Output V
CCIO_SDM
Input V
CCIO_SDM
Input V
CCIO_SDM
Output V
CCIO_SDM
Intel ® Agilex ™ Configuration User Guide
,
continued...
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