Intel Agilex Configuration User Manual page 20

If your design includes any initialized Intel Hyperflex
Gating Intel Hyperflex registers with the
instantiate the Reset Release IP in your design, the SDM drives the
consume any FPGA fabric resources, but does require routing resources. You can find the Reset Release IP in the Intel
Quartus Prime and Platform Designer IP Catalogs under Basic Functions/Configuration and Programming.
Figure 6. Intel Agilex Reset Release IP nINIT_DONE Internal Connection
Intel ® Agilex ™ Configuration User Guide
20
™
registers, these registers must be gated using the
signal prevents these registers from losing their initial value. When you
nINIT_DONE
nINIT_DONE
2. Intel Agilex Configuration Details
UG-20205 | 2019.04.03
nINIT_DONE
signal. Consequently, the IP does not
signal.
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