Intel Agilex Configuration User Manual page 6

Table 1. Intel Agilex Configuration Data Width, Clock Rates, and Data Rates
Configuration Scheme
Passive
Active
Avalon-ST
The Avalon-ST configuration scheme is a passive configuration scheme. Avalon-ST is the fastest configuration scheme for Intel
Agilex devices. Avalon-ST configuration supports x8, x16, and x32 modes. The x16 and x32 bit modes use general-purpose
I/Os (GPIOs) for configuration. The x8 bit mode uses dedicated SDM I/O pins.
Avalon-ST supports backpressure using the
incoming bitstream varies, backpressure support is necessary to transfer data to the Intel Agilex device. For more information
about the Avalon-ST refer to the Avalon Interface Specifications.
JTAG
You can configure the Intel Agilex device using the dedicated JTAG pins. The JTAG port provides seamless access to many
useful tools and functions. In addition to configuring the Intel Agilex, the JTAG port is used for debugging with Signal Tap or
the System Console tools.
The JTAG port has the highest priority and overrides the
device over JTAG even if the
CvP
CvP uses an external PCIe* host device as a Root Port to configure the Intel Agilex device over the PCIe link. You can specify
up to a x16 PCIe link. Intel Agilex devices support two CvP modes, CvP init and CvP update.
Intel ® Agilex ™ Configuration User Guide
6
Avalon-ST
JTAG
Configuration via Protocol (CvP)
SD/MMC
AS - fast mode
AS - normal mode
AVST_READY
pin specify a different configuration scheme unless you disabled JTAG for security reasons.
MSEL
Data Width (bits)
32
16
8
1
x1, x2, x4, x8, x16 lanes
4/8
4
4
and pins. Because the time to decompress the
AVST_VALID
pin settings. Consequently, you can configure the Intel Agilex
MSEL
® ™
1. Intel Agilex Configuration Overview
UG-20205 | 2019.04.03
MSEL[2:0]
000
101
110
111
001
100
001
011
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