Intel Agilex Configuration User Manual page 38

Optionally, you can monitor the
configuration process is complete.
If you use the PFL II IP core as the configuration host, you can use the Intel Quartus Prime software to store the binary
configuration data to the flash memory through the PFL II IP core.
If you use the Avalon-ST Adapter IP core as part of the configuration host, set the Ready Latency value between 1- 6.
Avalon-ST x8 configuration scheme uses the SDM pins only. Avalon-ST x16 and x32 configuration scheme only use dual-
purpose I/O pins that you can use as general-purpose I/O pins after configuration.
Related Information
Avalon Interface Specifications
Intel ® Agilex ™ Configuration User Guide
38
signal to indicate the flash has sent all the data to FPGA or to indicate the
CONF_DONE
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
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